The present invention relates generally to computer systems and, more specifically, to computer system clock synchronization.
A conventional computer system includes a clock that controls the timing of the computer functions it performs. Such a computer system may have two clocks controlling the functions performed by two separate clock domains. For example, a computer system may have a primary clock controlling a clock domain devoted to processor functions and a secondary clock controlling a clock domain devoted to input/output functions. In such an environment, the primary clock and secondary clock must be synchronized to function correctly.
Such a computer system typically is implemented on a circuit board. The circuit board may contain a subsystem implemented with a chip such as an ASIC (Application Specific Integrated Circuit) that has its own internal clock control. In such a system, the ASIC may also have two internal primary and secondary clocks. In such a system, the external system clocks must be synchronized with the internal ASIC clocks. Also, the internal primary and secondary clocks must be synchronized to function correctly. Thus, a means is desirable for providing an efficient and effective synchronization of all four clock domains.